Author: Iain Bate (University of York, United Kingdom)
Date: June 10th
Time: 9:30 – 10:00 (CEST)
Timing Analysis and Verification of Multi-core Real-Time Systems for Aerospace Applications
Multi-core processors are both needed by industry due to enhanced functionality in systems but also being forced on them by the available supply chain. Regulatory authorities have provided some guidance on achieving certification when multi-cores are used. The current recommendations suggest simple devices with low numbers of cores. The guidance also suggests that interference channels are both understood and their potential effects mitigated. Our work has been driven by our usual mantra design-for-predictability and design-for-safety. In previous projects, we performed significant work on multi-core timing analysis and on scheduling approaches for mixed-criticality scheduling. This introduced us to the significant challenges of creating robust and justifiable analysis. The result was that systematic testing and careful statistical analysis is needed for the evidence gained to be useful. Important lessons include the way the software is written and the way the platform is configured is key to getting useful results.
More recently, we have started two projects: HiClass for UK civil avionics and MOCHA for Huawei. In this talk, I will concentrate on HiClass however many of the principles apply to both projects. The first question we are normally asked is what platform should be chosen. This includes which processor family, which processor variant, which RTOS if any, and how all these should be configured. Evidence suggests all these questions have a fundamental effect on what follows but this is very much a chicken and egg problem. Once these decisions have been taken, an appropriate understanding of interference channels needs to be attained and then this knowledge used in the scheduling and allocation of the software. Predictability is important here however maintainability is going to be fundamental. In this talk, we will briefly introduce the pillars of our work which are selection and configuration of platforms, multi-core timing analysis, and scheduling and timing analysis.
Dr Iain Bate is a Reader within the Real-Time Systems (RTS) Research Group at York. His main interests include scheduling and timing analysis, and design assurance to achieve dependable operation even when there are complex failures. His original doctoral work on scheduling and timing analysis was first patented and then adopted by Rolls-Royce for use on current aircraft projects. His work on timing analysis has been used on a large fast jet project. More recently he has worked on applying the principles of Dependable Real-Time Systems (DRTS) to more complex systems such as multi-core based systems, automotive systems and Wireless Sensor Networks (WSN) including for environmental monitoring. In particular he has concentrated on reducing the errors in systems through the building of systematic methods based around multivariate statistical models. Dr Bate has published over 200 papers and 30 industrial reports. He has recently secured nearly £2 million from Innovate UK, for HiClass, and Huawei (project MOCHA) to apply his current research to the next generation of systems. Dr Bate is heavily involved in the appropriate communities including being an Editor-in-Chief of leading international journals for more than 15 years, a member of all leading Program Committees in his research field, Program Chair of three leading international conferences, and a regular keynote speaker and guest researcher at other institutions. He has also been influential in both certification guidance and industrial practice. He is part of the UK’s multi-core working group.